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Programming Future HPC Machines

Gilbert Netzer, PDC

To deliver high-performance end-user applications, software developers have to become increasingly aware of the micro-architecture innovations used in modern high-performance computing (HPC) hardware – this also applies to the replacement for Beskow, PDC's current main system. So, in addition to a workshop about the ARM HPC ecosystem , PDC hosted two webinars on programming NEC's and Intel's upcoming HPC solutions.

On the 14th of February, NEC presented their latest product in a long line of vector computers, the SX Aurora TSUBASA. The accompanying compiler, which is capable of understanding both FORTRAN and C++, attempts to extract suitable vector operations from the nested loop structures often found in scientific applications. As demonstrated in examples, programmers can get feedback in the form of detailed vectorization reports and run-time profiling information that helps to restructure the source code into recognizable idioms while avoiding stumbling blocks like unsuitable function calls.

A webinar on the 24th of March covered how to program Intel's entry into the discrete graphics processing unit (GPU) market, which is known as the Xe architecture. A cornerstone of Intel's strategy is a new software stack called oneAPI that offers a new programming model, data parallel C++, which is an extended version of ISO C++ based on the Khronos SYCL and community efforts.

In addition to working with GPUs, oneAPI is able to target Intel's CPUs, Field Programmable Gate Arrays (FPGAs) and other accelerator technologies. The package also includes further programming languages like OpenCL, as well as support for OpenMP target offload directives in both C++ and FORTRAN. Attendees could try out a beta version of this new software product in hands-on exercises using Intel's DevCloud.