Towards Peak Performance with IBM POWER3

Contents

1. Towards Peak Performance with IBM POWER3
   
2. Topics
   
3. The POWER3 Residency at Austin, Texas
   
4. RED BOOK: SG24-5155-00 RS/6000 Scientific and Technical Computing: POWER3 Intro
   
5. RS/6000 Processor Roadmap
   
6. POWER3 Architecture
   
7. Stride and Data Cache Structure
   
8. Stride in Fortran loops
   
9. Data Cache structure
   
10. Effects of stride on performance
    
11. The 4-Way Set Associative POWER2 Data Cache
    
12. The 128-Way Set Associative POWER3 Data Cache
    
13. Translation Lookaside Buffer (TLB)
    
14. 
    
15. 
    
16. Superscalar Floating Point Units
    
17. POWER3 Floating Point Unit - Superscalar Pipeline
    
18. IBM XL Fortran - new with V5
    
19. XLF V5 64-bit Support
    
20. IBM XLF V5 Compiler Optimisation Improvements
    
21. XLF V5 Compiler - SMP support
    
22. Compiling and linking for SMP
    
23. XLF V5 SMP Directives
    
24. Tuning for Maximum Megaflops
    
25. Hand tuning techniques
    
26. "Common sense" example
    
27. Sequential processing
    
28. M x N unrolling (matrix multiply)
    
29. PERFORMANCE Recent Customer Benchmark
    
30. Benchmark Performance POWER3 vs POWER2
    
31. Benchmark Performance XLF V5 vs XLF V3
    
32. SMP Performance: Throughput
    
33. XLF V5 SMP Performance 2-way parallel
    
34. MPI
    
35. MPI vs XLF V5 parallelisation within an SMP
    
36. HPF "High Performance Fortran"
    
37. MPI within an SMP
    
38. SMP nodes in RS/6000 SP
    
39. SMP/SP programming paradigms
    
40. SMP/SP paradigms